1. Technical Field
The present application relates generally to an improved information processing device. More specifically, the present application is directed to an apparatus and method for controlling asynchronous clock domains to perform synchronous operations.
2. Description of Related Art
Highly integrated microprocessor and system-on-a-chip integrated circuits contain many different functional elements. The core logic of microprocessors run with gigahertz clocks. However, when input/output (I/O) and memory devices are incorporated on the same chip, these devices will require different clocking requirements. For a scan based design, i.e. a design in which data is scanned through the latch elements of the various functional elements of the microprocessor or system-on-a-chip, the different clocking requirements creates asynchronous boundaries between the core logic and the other functional elements. Scanning across asynchronous clock boundaries is problematic because latch setup and hold times cannot be established reliably between the two clocking environments.
This is especially a problem with power on reset (POR) and manufacturing test sequences. During a power on reset sequence, the desire is to have all digital logic running on the same clock. This will allow the POR engine to scan all latch elements to initialize the chip to a known state. A similar requirement for the latches to run on the same clock is present for performing manufacturing test sequences. This, however, is not possible with microprocessors or systems-on-a chip that have different clocking domains on the chip. As a result, during a POR or manufacturing test, the POR logic and test logic must treat each clock domain separately. Thus, the design and implementation of a POR engine and test circuitry becomes more complex in order to properly performing a POR or manufacturing test sequence.